Integrated circuits contain several physical layers of circuit structures. The physical layers may include, for example, a layer of metal interconnects formed by a copper damascene process, which uses a copper chemical mechanical polish (CMP) process. The circuit structures include the metal interconnects which provide electrical connections between components of the integrated circuit. In other examples, the physical layers may include an active area layer laterally surrounded by a layer of field oxide formed by a shallow trench isolation (STI) process which uses an oxide CMP process, a layer of gates for metal oxide semiconductor (MOS) transistors formed by a polycrystalline silicon reactive ion etch (RIE) process, or a layer of metal interconnects formed by an aluminum ME process. The physical layers are formed using etch masks on the integrated circuit, which are patterned using photolithographic processes. CMP processes, ME processes, photolithographic processes, and other fabrication processes, have higher process latitude when the physical layer has increased uniformity across the integrated circuit. Functional structures are understood to be structures of the physical layers which are included in the functional design of the integrated circuit and may be related to operation of the integrated circuit. Other structures of the physical layers may include alignment marks, die marks, and test structures.
The process masks to form the physical layers are formed using photomasks which have mask elements corresponding to the structures of the physical layers. The photomasks are formed using layout files which include geometries corresponding to the mask elements of the photomasks. It is common to add fill geometries for fill structures to the layout files for making photomasks used in fabricating the integrated circuits. Fill geometries are sometimes referred to as fill pattern, dummy geometries or dummy pattern. The fill structures are not directly electrically connected to components of the integrated circuit. The fill geometries are added to improve pattern uniformity. Attaining uniform densities among various devices fabricated using a common process sequence has been problematic, thus undesirably reducing process latitude for the relevant operations.